Fast Key-Value Lookups with Node Tracker

Lookup operations for in-memory databases are heavily memory bound, because they often rely on pointer-chasing linked data structure traversals. They also have many branches that are hard-to-predict due to random key lookups. In this study, we show that although cache misses are the primary bottleneck for these applications, without a method for eliminating the branch mispredictions only a small fraction of the performance benefit is achieved through prefetching alone. We propose the Node Tracker (NT), a novel programmable prefetcher/pre-execution unit that is highly effective in exploiting inter key-lookup parallelism to improve single-thread performance. We extend NT with branch outcome streaming (BOS) to reduce branch mispredictions and show that this achieves an extra 3× speedup. Finally, we evaluate the NT as a pre-execution unit and demonstrate that we can further improve the performance in both single- and multi-threaded execution modes. Our results show that, on average, NT improves single-thread performance by 4.1× when used as a prefetcher; 11.9× as a prefetcher with BOS; 14.9× as a pre-execution unit and 18.8× as a pre-execution unit with BOS. Finally, with 24 cores of the latter version, we achieve a speedup of 203× and 11× over the single-core and 24-core baselines, respectively

Uniprocessor performance enhancement through adaptive clock frequency control

Uniprocessor designs have always assumed worst-case operating conditions to set the operating clock frequency and, hence, performance. However, much more performance can be obtained under typical operating conditions through experimentation, but such increased frequency operation is subject to the possibility of system failure and, hence, data loss/ corruption. Further, mobile CPUs such as those in cell phones/internet browsers do not adapt to their current surroundings (varying temperature conditions, etc.) so as to increase or decrease operating frequency to maximize performance and/or allow operation under extreme conditions. We present a digital hardware design technique realizing adaptive clock-frequency performance-enhancing digital hardware; the technique can be tuned to approximate performance maximization. The cost is low and the design is straightforward. Experiments are presented evaluating such a design in a pipelined uniprocessor realized in a Field Programmable Gate Array (FPGA). © 2005 IEEE

Going beyond worst-case specs with TEAtime

The timing-error-avoidance method continuously modulates a computer-system clock\u27s operating frequency to avoid timing errors even when presented with worst-case scenarios. The timing-error-avoidance prototype provides a circuit and system solution to such problems for synchronous digital systems. TEAtime has demonstrated much better performance than classically designed systems and also adapts well to varying temperature and supply-voltage conditions

The URI integrated computer engineering design (ICED) curriculum: Progress report

The University of Rhode Island started the ICED curriculum in the Fall of 1997. The key feature of ICED is a substantial 2-3 year long project tying together important but normally disjoint computer engineering concepts across the major. The students learn how to make critical hardware/software tradeoffs with long-term implications. Courses in processor design, compiler design and networks are required, and tied together through the major project. This keeps students motivated in novel ways: they enjoy discovering the implications of decisions made in one area, across all other areas over the span of years. This paper reports on the status and progress of ICED after two years of startup operation. Some custom hardware was required for the curriculum; these lab stations have now been built and are currently being tested. In our original NSF grant we noted the need for additional funds to build this hardware and otherwise equip more lab stations; we applied for and received these funds from the Champlin Foundations of Rhode Island in 1998/9. The students have received the new curriculum enthusiastically and have learned much. It has also been a learning experience for the faculty involved. We are immediately plowing what we learn back into the design of ICED and its core courses, in order to fully achieve and enhance our curricular goals. The paper includes descriptions and documentation of all of the above

The integrated computer engineering design (ICED) curriculum

A new undergraduate computer engineering curriculum, ICED, is being introduced at the University of Rhode Island. The main feature of the curriculum is a design project spanning the last three years of the major. This gives continuity to a student\u27s studies: they will always know why they are learning a particular topic, and how it fits into the big picture. It also introduces them to long-term projects, and the requisite good documentation and communication habits necessary for its completion. The project to be undertaken is the design, simulation and construction of a computer and its compiler, including the design of its instruction set. Further, the various students \u27 computers will be networked together during the final integration phase of the project. Thus, several aspects of computer architecture are treated in depth. Students will learn to make hardware/software design tradeoffs, as well as get hands-on experience with hardware. A key element of the design experience is the use of modern CAD tools. The Mentor Graphics CAD tool suite will be used throughout the curriculum. By standardizing on one set of tools, the time for the students to learn the tools is amortized over the entire curriculum. The curriculum has received funding from the National Science Foundation, and has been formally approved by the University. Students began the curriculum in Fall, 1997. This paper gives the rationale of ICED in depth, and describes the core courses, their activities and use of CAD tools, and how they interrelate to achieve the goals. The current status of ICED is also reviewed